Memory for implementing at least one of reading or writing command
US11676642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Oct 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.