Patent · US Active

Semiconductor structure and fabrication method thereof

US11676865B2 · kind B2 · utility

0Cited by
1References
17Claims
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Key dates

Filing dateApr 29, 2021
Grant dateJun 13, 2023
Priority date
Expiry dateJun 30, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/6728

Abstract

Semiconductor structures and fabrication methods thereof are provided. The method includes providing a substrate; forming a stacked material structure on the substrate; and forming trenches in the stacked material structure. Bottoms of the trenches are in the first material layer, the trenches are arranged along a first direction and form an initial stacked structure sequentially including an initial first layer, an initial second layer and an initial third layer. The method also includes etching the initial third layer to form transitional third layers arranged along a second direction perpendicular to the first direction; removing a portion of the initial first layer and a portion of the initial second layer of the initial stacked structure at two sides along the second direction to form a stacked structure including a first layer, a second layer and the transitional third layers; and forming a gate structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.