Patent · US Active

Semiconductor die package with warpage management and process for forming such

US11676876B2 · kind B2 · utility

0Cited by

0References

26Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ziyin Lin · Chandler, US
Elizabeth Nofen · Gilbert, US
Vipul V. Mehta · Chandler, US
Taylor Gaines · Chandler, US

Key dates

Filing date	Aug 30, 2019
Grant date	Jun 13, 2023
Priority date	—
Expiry date	Oct 11, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.