Semiconductor devices
US11676888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2020 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Oct 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device including a stack of layers defining a first conductor pattern at a first level of the stack and one or more semiconductor channels in respective regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack. The stack includes at least two insulator patterns over which the first level or second level conductor patterns is formed. A first insulator pattern occupies one or more semiconductor channel regions to provide the dielectric. The second insulator pattern defines one or more windows in the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern. The second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.