FPGA-efficient directional two-dimensional router
US11677662B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Mar 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.