Droop detection
US11680965B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2022 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Jul 22, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.