Semiconductor layout with different row heights
US11682665B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | Apr 22, 2020 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Mar 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.