System and method for correcting overlay errors in a lithographic process
US11687010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Feb 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/682
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
As feature sizes of semiconductor chips shrink there is a need for tighter overlay between layers in a lithography process. This means more advanced and larger overlay corrections may be necessary to ensure that die are properly manufactured into chips, especially in reconstituted substrates where the die can shift in the process of creating the substrate. Systems and methods for correcting these overlay errors in a lithographic process are provided. Additional rotation (theta) and projected image size (mag) corrections can be made to correct overlay errors present in reconstituted substrates by adjusting the stage and the reticle. Furthermore, these adjustments can be made allowing site-by-site or zone-by-zone corrections instead of a one-time adjustment of the reticle chuck as has been done in the past. These corrections can alleviate some of the issues associated with fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.