Power supply rejection enhancer
US11687104B2 · kind B2 · utility
0Cited by
13References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Aug 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/16
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.