System and methods for on-chip memory (OCM) port throttling for machine learning operations
US11687144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2022 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Feb 11, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new approach contemplates systems and methods to support control of power consumption of a memory on a chip by throttling port access requests to the memory via a memory arbiter based on a one or more programmable parameters. The memory arbiter is configured to restrict the number of ports being used to access the memory at the same time to be less than the available ports of the memory, thereby enabling adaptive power control of the chip. Two port throttling schemes are enabled—strict port throttling, which throttles the number of ports granted for memory access to be no more than a user-configured maximum throttle port number, and leaky bucket port throttling, which throttles the number of ports granted for the memory access down to be within a range based on a number of credit tokens maintained in a credit register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.