FPGA board memory data reading method and apparatus, and medium
US11687242B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Feb 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.