Methods and apparatus for cache-aware task scheduling in a symmetric multi-processing (SMP) environment
US11687364B2 · kind B2 · utility
0Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2020 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Apr 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is configured to collect information related to a first activity and analyze the collected information to determine decision data. The information is stored in a first list of the source processing core for scheduling execution of the activity by a destination processing core to avoid cache misses. The source processing core is configured to transmit information related to the decision data using an interrupt, to a second list associated with a scheduler of the destination processing core, if the destination processing core is currently executing a second activity having a lower priority than the first activity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.