Method for controlling a technical apparatus
US11687398B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Dec 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3089
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The architecture includes four largely independent subsystems which are arranged hierarchically and each form an isolated Fault-Containment Unit (FCU). At the top of the hierarchy is a secure subsystem, the Fault-Tolerant Decision Subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are insecure because they contain complex software executed on non-fault-tolerant hardware. Experience has shown that it is difficult to find all design errors in a complex software system and to prevent an intrusion. The redundancy and diversity inherent in this architecture masks every error—even a Byzantine error—of an insecure subsystem in such a way that no safety-critical failure can occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.