Centralized SRAM error location detection and recovery mechanism
US11687405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Dec 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes two or more memory devices and a controller coupled to the two or more memory devices. The controller is configured to program data to one or more memory devices of the two or more memory devices, select one or more of the one or more memory devices to have additional ECC for the data of the one or more memory devices, program the additional ECC to a first memory device. The data is programmed with error correction code (ECC). The first memory device is distinct from the one or more memory devices. The first memory device is disposed in a central module, where the central module includes additional decoding capability. The additional ECC and the corresponding data with ECC are concatenated and decoded for additional error correction capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.