Acceleration unit for a deep learning engine
US11687762B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 20, 2019 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Apr 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.