Interposer and semiconductor package including the same
US11688656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2020 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Nov 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.