Analogue switch arrangement
US11689199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2022 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jun 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.