Clock frequency monitoring for a phase-locked loop based design

US11689206B1 · kind B1 · utility

Assignee

• NXP B.V. · NL

Inventors

• Ulrich Moehlmann · Hamburg, DE
• Andreas Lentz · Buchholz, DE

Key dates

• Filing date: Mar 4, 2022
• Grant date: Jun 27, 2023
• Expiry date: Mar 4, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L2207/50
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A method for clock frequency monitoring for a Phase-Locked Loop (PLL) based design includes determining a present operating point of an oscillator of the PLL based design, wherein the oscillator generates a present frequency in response to the present operating point. The present operating point of the oscillator is compared to a comparison range defined by a plurality of reference operating points, wherein the oscillator generates a nominal reference frequency in response to a nominal one of the plurality of reference operating points and the comparison range is further defined by a manufacturing process range, an operating voltage range and an operating temperature range. An action is performed in response to the present operating point being outside of the comparison range.