Device-tailored model-free error correction in quantum processors
US11689223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2018 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Sep 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Model-free error correction in quantum processors is provided, allowing tailoring to individual devices. In various embodiments, a quantum circuit is configured according to a plurality of configuration parameters. The quantum circuit comprises an encoding circuit and a decoding circuit. Each of a plurality of training states is input to the quantum circuit. The encoding circuit is applied to each of the plurality of training states and to a plurality of input syndrome qubits to produce encoded training states. The decoding circuit is applied to each of the encoded training states to determine a plurality of outputs. A fidelity of the quantum circuit is measured for the plurality of training states based on the plurality of outputs. The fidelity is provided to a computing node. The computing node determines a plurality of optimized configuration parameters. The optimized configuration parameters maximize the accuracy of the quantum circuit for the plurality of training states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.