Patterning method for preparing top-gate, bottom-contact organic field effect transistors
US11690236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2022 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Feb 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/231
Abstract
The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer block B is attached to the polymer block A, and wherein at least 60 mol % of the repeat units of polymer block B are selected from the group consisting of Formulas (1A), (1B), (…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.