Silicon photonics collimator for wafer level assembly
US11693169B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Mar 8, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J14/023
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments are disclosed for providing a silicon photonics collimator for wafer level assembly. An example apparatus includes a silicon photonics (SiP) device and a micro-optical passive element. The SiP device comprises a set of optical waveguides. The micro-optical passive element is mounted on an edge of a cavity etched into a silicon surface of the SiP device. Furthermore, the micro-optical passive element is configured to direct optical signals between the set of optical waveguides and an external optical element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.