Multi-die power management in SoCs
US11693472B2 · kind B2 · utility
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5References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Feb 21, 2022 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Feb 21, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.