Precise longitudinal monitoring of memory operations
US11693588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Apr 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.