Semiconductor memory device with mapping factor generating unit for improving reliability
US11693786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Oct 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.