Dielectric molded indium bump formation and INP planarization
US11694981B2 · kind B2 · utility
0Cited by
0References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2019 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Mar 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosed technique may be used to electrically and physically connect semiconductor wafers. The wafer may utilize a thick dielectric. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.