Test pad structure of chip
US11694983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Aug 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/9211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.