True single phase clock (TSPC) based latch array
US11695393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Nov 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.