Digital timer delay line with sub-sample accuracy
US11695399B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Jan 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present document relates to a timer which is counter-based and uses an asynchronous circuitry to improve the accuracy between the available clock cycles. In particular, a timer is presented which may comprise a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal. The first timer circuit may be configured to determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.