Semiconductor device
US11695415B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Dec 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.