Logic-in-memory inverter using feedback field-effect transistor
US11695420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Feb 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage VOUT that changes depending on a level of an input voltage VIN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage VSS is input to a source region of the nanostructure and a drain voltage VDD is input to a source region of the metal oxide semiconductor field-effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.