Digital signal processor/network synchronization
US11695537B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Jun 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.