On-chip virtual oscilloscope using high-speed receiver sampler readback
US11695601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Aug 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.