Semiconductor memory device
US11696434B2 · kind B2 · utility
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6References
20Claims
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Key dates
| Filing date | Apr 27, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Jul 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.