Geometries for mitigating artifacts in see-through pixel arrays
US11698557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Aug 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136286
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed are dimming assemblies and display systems for reducing artifacts produced by optically-transmissive displays. A system may include a substrate upon which a plurality of electronic components are disposed. The electronic components may include a plurality of pixels, a plurality of conductors, and a plurality of circuit modules. The plurality of pixels may be arranged in a two-dimensional array, with each pixel having a two-dimensional geometry corresponding to a shape with at least one curved side. The plurality of conductors may be arranged adjacent to the plurality of pixels. The system may also include control circuitry electrically coupled to the plurality of conductors. The control circuitry may be configured to apply electrical signals to the plurality of circuit modules by way of the plurality of conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.