Patent · US Active

Fractional clock divider

US11698657B2 · kind B2 · utility

0Cited by

4References

20Claims

0Family size

Assignee

SHENZHEN GOODIX TECHNOLOGY CO., LTD. · CN

Inventors

Ahmed Emira · Mission Viejo, US
Mohamed Aboudina · San Diego, US
Faisal Hussien · San Diego, US

Key dates

Filing date	Mar 31, 2022
Grant date	Jul 11, 2023
Priority date	—
Expiry date	Mar 31, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH04B1/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A communication circuit is disclosed. The communication circuit includes a clock input, and a clock divider configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, where the clock divider is configured to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal, generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, where the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and generate the output clock signal based at least in part on the 2N unique phase shifted clock signals, and a mixer, configured to receive the output clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.