Selective deactivation of processing units for artificial neural networks

US11698672B2 · kind B2 · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Juergen Schirmer · Heidelberg, DE
• Andre Guntoro · Weil der Stadt, DE
• Armin Runge · Heidingsfeld, DE
• Christoph Schorn · Leonberg, DE
• Jaroslaw Topp
• Sebastian Vogel · Schaidt, DE

Key dates

• Filing date: Jun 3, 2019
• Grant date: Jul 11, 2023
• Expiry date: Jun 30, 2039

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A hardware architecture for an artificial neural network ANN. The ANN includes a consecutive series made up of an input layer, multiple processing layers, and an output layer. Each layer maps a set of input variables onto a set of output variables, and output variables of the input layer and of each processing layer are input variables of the particular layer that follows in the series. The hardware architecture includes a plurality of processing units. The implementation of each layer is split among at least two of the processing units, and at least one resettable switch-off device is provided via which at least one processing unit is selectively deactivatable, independently of the input variables supplied to it, in such a way that at least one further processing unit remains activated in all layers whose implementation is contributed to by this processing unit.