Computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines
US11698869B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2022 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Mar 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The subject application relates to computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines. Apparatuses, systems, and techniques are described for computing an authentication tag for a data transfer when the data transfer is scheduled as partial transfers across a specified number of direct memory access (DMA) engines. An orchestration circuit stores partial authentication tags, computed by the DMA engines, and corresponding adjustment exponents during one or more rounds in which the partial transfers are scheduled and processed by the specified number of DMA engines. During a last round, a combined authentication tag can be computed based on the partial authentication tags and the corresponding adjustment exponents stored by the orchestration circuit during the rounds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.