Method for PRP/SGL handling for out-of-order NVME controllers
US11698871B2 · kind B2 · utility
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Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Sep 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.