Peripheral access on a secure-aware bus system
US11698995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Oct 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated-circuit device comprises a processor, a peripheral component, a bus system, connected to the processor and to the peripheral component, and configured to carry bus transactions; and hardware filter logic. The bus system is configured to carry security-state signals for distinguishing between secure and non-secure bus transactions. The peripheral component comprises a register interface, accessible over the bus system, and comprising a hardware register and a direct-memory-access (DMA) controller for initiating bus transactions on the bus system. The peripheral component supports a secure-in-and-non-secure-out state in which the hardware filter logic is configured to prevent non-secure bus transactions from accessing the hardware register of the peripheral component, but to allow secure bus transactions to access the peripheral component. The peripheral component is configured to allow an incoming secure bus transaction to access the hardware register and to initiate a bus transaction as non-secure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.