Coverage based microelectronic circuit, and method for providing a design of a microelectronic circuit

US11699012B2 · kind B2 · utility

Assignee

• MINIMA PROCESSOR OY · FI

Inventor

• Navneet Gupta · Ghaziabad, IN

Key dates

• Filing date: Nov 27, 2018
• Grant date: Jul 11, 2023
• Expiry date: Feb 27, 2039

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.