Arithmetic processing apparatus and control method therefor
US11699067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2018 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Aug 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0464
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To allow arithmetic processing using a plurality of processing nodes to be executed with a smaller memory size, an arithmetic processing apparatus for executing processing using a hierarchical type network formed by the plurality of processing nodes, comprises: a storage unit configured to store a parameter used by each of the plurality of processing nodes for arithmetic processing and a calculation result of the arithmetic processing in each of the plurality of processing nodes; and a buffer control unit configured to switch, based on a configuration of the hierarchical type network, a buffer system of the parameter and the calculation result in the storage unit in at least one layer of the hierarchical type network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.