Display panel and display device with reduced charge accumulation in semiconductor layer
US11699373B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 5, 2021 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Jul 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel and a display device are provided in the present disclosure. The display panel, having a display region and a frame region outside the display region, includes a base substrate; a buffer layer on a side of the base substrate, where the buffer layer includes an a-Si layer; a semiconductor layer on a side of the buffer layer away from the base substrate; an insulation layer on a side of the semiconductor layer away from the base substrate; and a power signal layer on a side of the insulation layer away from the base substrate. The power signal layer includes a plurality of first power voltage lines in the display region; and the power signal layer is electrically connected to a power signal terminal which alternately outputs a positive voltage signal and a negative voltage signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.