Phase locked loop generating adaptive driving voltage and related operating method
US11700005B2 · kind B2 · utility
2Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Nov 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.