Receiving circuit of deserializer
US11700155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Feb 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0292
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.