Efficient storage architecture for high speed packet capture
US11704063B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Jan 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/134
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment may involve a network interface module; volatile memory configured to temporarily store data packets received from the network interface module; high-speed non-volatile memory; an interface connecting to low-speed non-volatile memory; a first set of processors configured to perform a first set of operations that involve: (i) reading the data packets from the volatile memory, (ii) arranging the data packets into chunks, each chunk containing a respective plurality of the data packets, and (iii) writing the chunks to the high-speed non-volatile memory; and a second set of processors configured to perform a second set of operations in parallel to the first set of operations, where the second set of operations involve: (i) reading the chunks from the high-speed non-volatile memory, (ii) compressing the chunks, (iii) arranging the chunks into blocks, each block containing a respective plurality of the chunks, and (iv) writing the blocks to the low-speed non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.