Error avoidance in memory device
US11704211B1 · kind B1 · utility
3Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Dec 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for avoiding uncorrectable errors in a memory device can include detecting a correctable error pattern of a memory page of a memory device, and determining that the correctable error pattern of the memory page satisfies a page migration condition. Upon satisfying the page migration condition, write accesses to the memory page are prevented from reaching a memory controller of the memory device. The contents of the memory page are then migrated to a reserved page, and a mapping table is updated to replace accesses to the memory page with accesses to the reserved page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.