System and method for fast and accurate netlist to RTL reverse engineering
US11704460B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Jun 9, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Sep 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide for reverse engineering of integrated circuits (ICs) for design verification. In example embodiments, an apparatus receives a gate-level netlist for an integrated circuit (IC), generates a list of equivalence classes related to signals included in the gate-level netlist, determines control signals of the gate-level netlist based at least in part on the list of equivalence classes, determines a logic flow of a finite state transducer (FST) based at least in part on the control signals, and generates register transfer level (RTL) source code for the IC based on the FST.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.