Gate driving circuit and display panel
US11705085B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 9, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Jun 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving circuit and a display panel are provided. The gate driving circuit includes a plurality of shift register units as cascaded, and the plurality of shift register units as cascaded includes a first shift register unit including a first clock signal terminal, an (n+1)-th shift register unit including an (n+1)-th clock signal terminal, a second shift register unit including a second clock signal terminal, and an (n+2)-th shift register unit including an (n+2)-th clock signal terminal. The gate driving circuit further includes a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.