Method of manufacturing semiconductor device
US11705361B2 · kind B2 · utility
0Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Oct 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76889
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.