Semiconductor devices including an isolation insulating pattern with a first bottom surface, a second bottom surface, and a third bottom surface therebetween, where the third bottom surface has a different height than the first and second bottom surfaces
US11705451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Aug 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.